Cypress Semiconductor /psoc63 /USBFS0 /USBHOST /HOST_TOKEN

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Interpret as HOST_TOKEN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ENDPT0 (NONE)TKNEN0 (TGGL)TGGL

TKNEN=NONE

Description

Host Token Endpoint Register

Fields

ENDPT

These bits are used to specify an endpoint to send or receive data to or from the device. Note:

  • This bit isn’t initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to ‘1’.
TKNEN

These bits send a token according to the settings. After operation has been ended, the TKNEN bit is set to ‘000’, and the CMPIRQ bit of the Interrupt USB Host Register (INTR_USBHOST) is set to ‘1’. The settings of the TGGL and ENDPT bits are ignored when sending a SOF token. Notes:

  • This bit is set to the initial value when the RST bit of the Host Control 1 Register (HOST_CTL1) is set to ‘1’.
  • The PRE packet isn’t supported.
  • Do not set ‘100’ to the TKNEN bit when the SOFBUSY bit of the Host Status Register (HOST_STATUS) is ‘1’
  • Change the USB to the USB Host before writing data to this bit.
  • When issuing a token again after the token interrupt flag (CMPIRQ) has been set to ‘1’, wait for 3 cycles or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) was output, then write data to this bit.
  • Read the value of TKNEN bit if a new value is written in it .Continue writing in this bit until a retrieved value equals a new value written in. During this checking process, it is needed to prevent any interrupt.
  • Take the following steps when CMPIRQ bit of Interrupt USB Host Register (INTR_USBHOST) is set to ‘1’ by finishing IN token or Isochronous IN token.
  1. Read HS bit of Host Error Status Register (HOST_ERR), then set CMPIRQ bit to ‘0’.
  2. Set EPn bit of Host DMA Enable Register (HOST_DMA_ENBL) (n=1 or 2) to ‘1’ if HS bit of Host Error Status Register (HOST_ERR) is equal to ‘00’ and wait until EPn bit of Host DMA Data Request Register (HOST_DMA_DREQ) changes to ‘1’. Finish the IN token processing if HS bit is not equal to ‘00’.
  3. Read the received data if EPn bit of Host DMA Data Requet (HOST_DMA_DREQ) (n=1 or 2) changes to ‘1’.

0 (NONE): Sends no data.

1 (SETUP): Sends SETUP token.

2 (IN): Sends IN token.

3 (OUT): Sends OUT token.

4 (SOF): Sends SOF token.

5 (ISO_IN): Sends Isochronous IN.

6 (ISO_OUT): Sends Isochronous OUT.

7 (RSV): N/A

TGGL

This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving toggle data, received toggle data is compared with the toggle data of this bit to verify whether or not an error occurs. ‘0’ : DATA0 ‘1’ : DATA1 Notes:

  • This bit isn’t initialized even if the RST bit of the Host Control 1 Register (HOST_CTL1) is set to ‘1’.
  • Set this bit when the TKNEN bit of the Host Token Endpoint Register (HOST_TOKEN) is ‘000’.

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